Nā hale waihona puke i kākau ʻia ma SystemVerilog

cheshire

ʻO kahi Linux-hiki 64-bit RISC-V SoC i kūkulu ʻia a puni CVA6 (e ka pulp-platform).
  • 44
  • GNU General Public License v3.0

C128_MiSTer

  • 35

wd65c02

E hoʻokō pololei i ka FPGA o nā ʻano like ʻole 6502 CPU.
  • 23
  • GNU General Public License v3.0 only

verilog-ext

Nā Hoʻonui Verilog no nā Emacs.
  • 23
  • GNU General Public License v3.0 only

DDR4_controller

  • 22
  • Apache License 2.0

mil1553-spi

MIL-STD-1553 <->Alahaka SPI.
  • 21
  • MIT

cortex-m0-soft-microcontroller

Hoʻokomo ʻia ka microcontroller palupalu o kahi ARM Cortex-M0.
  • 18
  • MIT

Tiny_But_Mighty_I2C_Master_Verilog

I2C Master Verilog module.
  • 16
  • GNU General Public License v3.0 only

FPGA-Video-Processing

ʻO ka hoʻoili wikiō maoli me nā kānana Gaussian + Sobel e huli ana iā Artix-7 FPGA.
  • 15

dnn-engine

AXI-Stream Universal DNN Engine me Novel Dataflow hiki i ka 70.7 Gops/mm2 ma TSMC 65nm GP no 8-bit VGG16.
  • 15

SVA-AXI4-FVIP

YosysHQ SVA AXI Waiwai.
  • 14
  • ISC

libsv

He kumu wehe, hoʻohālikelike ʻia ʻo SystemVerilog kikohoʻe IP waihona.
  • 13
  • MIT

ndk-app-minimal

ʻO ka noi liʻiliʻi e pili ana i ka Network Development Kit (NDK) no nā kāleka FPGA.
  • 13
  • BSD 3-clause "New" or "Revised"

clic

ʻO RISC-V ka mea hoʻoponopono hoʻopau wikiwiki (e ka pulp-platform).
  • 11
  • Apache License 2.0

rggen-sv-rtl

Nā modules SystemVerilog RTL maʻamau no RgGen.
  • 9
  • MIT

mips_cpu

Hoʻokahi pōʻaiapuni 32 bit MIPS.
  • 9

hardcloud

FPGA ma ke ʻano he OpenMP Offloading Device..
  • 9
  • Apache License 2.0

risc-v-single-cycle

ʻO kahi PPU Risc-V 32 bit PPU.
  • 8

rp32

Kaʻina hana RISC-V me CPI=1 (nā ʻōlelo aʻo i hoʻokō ʻia i hoʻokahi pōʻai uaki).
  • 6
  • Apache License 2.0

simple10GbaseR

FPGA haʻahaʻa latency 10GBASE-R PCS.
  • 4
  • MIT

Arithmetic-Circuits

Aia kēia waihona i nā modula like ʻole e hoʻokō i nā hana helu. (na GabbedT).
  • 2
  • MIT

v_fplib

Hale Waihona Puke Verilog FPU.
  • 1
  • GNU General Public License v3.0

picoMIPS

ʻO ka mea hana picoMIPS e hana ana i ka hoʻololi affine.
  • 1
  • MIT

RV32-Apogeo

He RISC-V 32 bits, 7-pae, Out Of Order, hoʻopuka hoʻokahi manaʻo speculative processor. Hoʻohana ke kumu i nā hoʻonui B, C, a me M. Loaʻa nā waihona I a me D..
  • 1
  • MIT

risc-v_pipelined_cpu

RISC-V CPU me kahi paipu 5-pae, i kākau ʻia ma SystemVerilog.
  • 0

FPGAprojects

Nā Verilog Codes no nā papahana FPGA aʻu i hana ai i ka makahiki 2019, me ka 5 pae pipelined MIPS CPU.
  • 0

TCB

Kaʻa kaʻa paʻa, paʻakikī haʻahaʻa, kaʻa kaʻa ʻōnaehana hana kiʻekiʻe..
  • 0
  • Apache License 2.0

basys3_fpga_sandbox

E aʻo i nā kumu o Systemverilog, testbench a me nā mea hou aku.
  • 0

osdr-q10

Nā faila hoʻolālā heleuma Orion, firmware, a me ka code FPGA..
  • 0