Nā hale waihona puke i kākau ʻia ma VHDL

spi-fpga

SPI haku a me SPI kauā no FPGA i kākau ʻia ma VHDL.
  • 132
  • MIT

ethernet_mac

ʻEkolu-mode (10/100/1000) piha-duplex FPGA ethernet MAC ma VHDL.
  • 126
  • GNU General Public License v3.0

w11

PDP-11/70 CPU kumu a me SoC.
  • 111
  • GNU General Public License v3.0 only

Rudi-RV32I

He CPU RISCV kumu mua e kākoʻo ana i nā ʻōlelo kuhikuhi RV32I, ma VHDL.
  • 98
  • MIT

sdram-fpga

He kumu FPGA no kahi mea hoʻoponopono SDRAM maʻalahi..
  • 96
  • MIT

deniser

ʻO Amiga Denise pani pani.
  • 82

dvb_fpga

Hoʻokō RTL o nā ʻāpana no DVB-S2.
  • 79
  • GNU General Public License v3.0

fpga_puf

: kī: Technology-agnostic Physical Unclonable Function (PUF) module hardware no kekahi FPGA..
  • 79
  • BSD 3-clause "New" or "Revised"

PipelineC-Graphics

Nā kiʻi hōʻikeʻike.
  • 77

AXI4

AXI4 piha, Lite, a me AxiStream mea hōʻoia. AXI4 Interface Master, Responder, a me nā ʻāpana hōʻoia hoʻomanaʻo. ʻO AxiStream transmitter a me nā mea hōʻoia hōʻoia.
  • 77
  • GNU General Public License v3.0

neoTRNG

🎲 ʻO kahi mea hoʻoheheʻe helu liʻiliʻi a me ke kahua kūʻokoʻa no kēlā me kēia FPGA..
  • 75
  • BSD 3-clause "New" or "Revised"

fpga-fft

ʻO kahi kumu hoʻoheheʻe FFT maikaʻi loa e pili ana i ka 4-step nui FFT algorithm a Bailey.
  • 71
  • GNU General Public License v3.0

uart-for-fpga

Hoʻoponopono UART maʻalahi no FPGA i kākau ʻia ma VHDL.
  • 69
  • MIT

CoPro6502

Hoʻokō FPGA o BBC Micro Co Processors (65C02, Z80, 6809, 68000, x86, ARM2, PDP-11, 32016).
  • 68
  • GNU General Public License v3.0 only

R3DUX

  • 58
  • GNU General Public License v3.0 only

mc1

He kamepiula (FPGA SoC) e pili ana i ka CPU MRISC32-A1.
  • 48
  • zlib

NN_RGB_FPGA

Hoʻolālā FPGA o kahi Pūnaewele Neural no ka ʻike kala.
  • 44
  • MIT

catapult-v3-smartnic-re

Ka palapala ʻana i nā papa Catapult v3 SmartNIC FPGA (Dragontails Peak & Longs Peak).
  • 40

neoapple2

ʻO ke awa o Stephen A. Edwards Apple2fpga iā PYNQ-Z1 (Xilinx Zynq FPGA), e hoʻohālike i kahi Apple II+..
  • 40

Apple-II_MiSTer

Apple II+ no MiSTer.
  • 40

neorv32-setups

📁 Nā papahana NEORV32 a me nā hoʻonohonoho hoʻohālike no nā FPGA like ʻole, nā papa a me nā kaulahao mea hana (open-source).
  • 37
  • BSD 3-clause "New" or "Revised"

fpu

IEEE 754 floating point waihona ma system-verilog a me vhdl (na taneroksuz).
  • 34
  • Apache License 2.0

vhdl-tutorial

  • 34
  • GNU General Public License v3.0 only

ZPUFlex

ʻO kahi ʻano ʻokoʻa i hoʻonohonoho pono ʻia a paʻa hoʻi o ka ZPU processor core.
  • 32

bonfire-cpu

FPGA hoʻokō pono RISC-V (RV32IM).
  • 31
  • GNU General Public License v3.0

C128_MiSTer

[Neʻe i: https://github.com/MiSTer-devel/C128_MiSTer] (na eriks5).
  • 30

a2i

Ua hoʻohana ʻia ke kumu A2I ma ke ʻano he kaʻina hana maʻamau no BlueGene/Q, ka mea pani i BlueGene/L a me BlueGene/P supercomputers (e OpenPOWERFoundation).
  • 25
  • GNU General Public License v3.0

FPGA-Vision

E aʻo e pili ana i ka hana kiʻi me kahi FPGA. Hōʻike nā haʻawina wikiō i ka algorithm a me ka hoʻokō ʻana i ka ʻike ala no ka hoʻokele kaʻa. Loaʻa nā lako lako maoli ma ke ʻano he lab mamao..
  • 25
  • GNU General Public License v3.0

fpga_torture

🔥 ʻenehana-agnostic FPGA stress-test: ka hoʻohana ʻana i ka loiloi kiʻekiʻe a me ka hoʻohana mana ikaika kiʻekiʻe.
  • 25
  • BSD 3-clause "New" or "Revised"

Compliance-Tests

Nā hoʻāʻo e loiloi i ke kākoʻo o nā hiʻohiʻona VHDL 2008 a me VHDL 2019.
  • 24
  • Apache License 2.0