Nā hale waihona puke i kākau ʻia ma VHDL

pyxhdl

Python Frontend No VHDL A me Verilog.
  • 7
  • GNU General Public License v3.0

SoC

ʻO Github Repo no ka papa FPGA i hoʻopili ʻia e Vincent Claes.
  • 7

rggen-sample

  • 7
  • MIT

REX_Classic

REX no TRS-80 Model 100, 102, 200.
  • 7

fiate

Lako Ho'o 'akomi Ho'ā 'o Fault Injection.
  • 6
  • Apache License 2.0

upduino-projects

Nā papahana VHDL like ʻole aʻu i hana ai no ka Upduino v2.0 a me v3.0.
  • 6
  • GNU General Public License v3.0 only

BYU_PYNQ_PR_Video_Pipeline_Hardware

BYU Pynq PR Video Pipeline Lako.
  • 6

cyc1000-rsu

ʻO ka papahana CYC1000 FPGA Remote System Upgrade.
  • 6
  • MIT

WARP_Core

ʻO Wilson AXI RISCV kaʻina hana kumu.
  • 6

hVHDL_fpga_interconnect

kaʻaahi interconnecting i kākau ʻia ma VHDL no ka loaʻa ʻana o ka ʻikepili ma nā modules FPGA.
  • 5
  • MIT

video_processing

ʻO ka hana wikiō maoli ma FPGA.
  • 4

hVHDL_gigabit_ethernet

VHDL waihona no ka synthesizable liʻiliʻi gigabit ethernet me RGMII interface, liʻiliʻi ethernet, ip a me udp poʻomanaʻo parsers.
  • 4
  • MIT

minitel2.0

Ke kūkulu ʻana i kahi ʻāpana kamepiula hou mai kahi minitel kahiko no nā noi domotic.
  • 4
  • GNU General Public License v3.0 only

rggen-vhdl-rtl

  • 4
  • MIT

vc_axi

  • 3

TectOH

Tectonics Open Hardware Sandbox.
  • 2
  • GNU Lesser General Public License v3.0 only

Xilinx-DPUV3.0-Vivado-Proj

Hoʻohui ʻia ʻo Deep Learning Processing Unit (DPU IP) me ka Application Processing Unit (APU) me ka hoʻohana ʻana (Zynq-7000 PS) ma Xilinx Vivado Design Suite.
  • 2

es4

Code no Tufts ES4 Intro to Digital Electronics.
  • 2
  • MIT

Arcade-MCR3_MiSTer

Arcade: Nā pāʻani ma waena o Midway MCR3.
  • 2

Smallpond

Hana ʻia ka hale hoʻolālā RISC hou ma CSE 490.
  • 2
  • MIT

BBC_DemiSTify

Ua hoʻemi ʻia ʻo BBC micro.
  • 0

sin_lut

Maʻalahi, papaʻaina ʻimi sine i hoʻohālikelike ʻia.
  • 0

VHDL_real_time_simulation

Pāhana maʻalahi no ka pou blog me nā hiʻohiʻona synthesizable o nā mea hoʻololi buck.
  • 0
  • MIT

TDP-11

  • 0

hlsVHDL_floating_point

  • 0
  • MIT

MultiCPU_Microprocessor

ʻO kēia ka papahana hope loa no CS-401 Computer Architecture. Ua kūkulu ʻia ka microprocessor me VHDL ma Xilinx Vivado. Ua hoʻoholo kaʻu hui e kūkulu i kahi mea e like me ka GPU hiki ke hana i nā helu maʻalahi i ka manawa like.
  • 0

EdgeDetectionAccelerator

FPGA-hoʻokumu ʻia ʻo Image Edge Detection Accelerator.
  • 0
  • MIT

MaquinaDeVendas

Projeto apresentado for obtenção de nota parcial and disciplina de Circuítos Digitais, da Universidade Tecnológica Federal do Paraná, campus Apucarana..
  • 0