Nā hale waihona puke i kākau ʻia ma VHDL
spi-to-axi-bridge
He alahaka SPI i AXI4-lite no ka hoʻopili maʻalahi ʻana o nā waihona hoʻopaʻa inoa airhdl me kekahi microcontroller.
- 21
- Apache License 2.0
neorv32-riscof
✔️Port o RISCOF e hōʻoia i ka hoʻohālikelike ʻana o ka RISC-V ISA o NEORV32 Processor.
- 19
- BSD 3-clause "New" or "Revised"
wb_spi_bridge
🌉 He alahaka Wishbone-to-SPI maopopo e kākoʻo ana iā Execute-In-Place (XIP).
- 19
- BSD 3-clause "New" or "Revised"
karabas-128
Karabas-128. ZX Spectrum 128k clone, ma muli o CPLD Altera EPM7128STC100.
- 18
- Do What The F*ck You Want To Public
pocket-cnn
CNN-to-FPGA-framework no CNN liʻiliʻi, i kākau ʻia ma VHDL a me Python.
- 16
- Mozilla Public License 2.0
Brutzelkarte_FPGA
ʻO ke code wehewehe ʻo Brutzelkarte FPGA ma VHDL.
- 13
- GNU General Public License v3.0 only
hVHDL_example_project
He papahana laʻana e hoʻohana ana i ka nui o nā manaʻo a me nā hiʻohiʻona o nā hale waihona puke hVHDL e like me nā modula makemakika paʻa a me ka floating point a ua kūkulu i nā palapala no nā FPGA maʻamau.
- 12
riscv-debug-dtm
🐛 JTAG debug transport module (DTM) - kūpono i ka RISC-V debug specification..
- 12
- BSD 3-clause "New" or "Revised"
hVHDL_fixed_point
ʻO ka waihona VHDL o nā hana makemakika kiʻekiʻe abstraction level synthesizable no ka hoʻonui, ka mahele a me ka hana hewa/cos a me ka hoʻololi abc i dq.
- 10
- MIT
neorv32-examples
ʻO kekahi mau hiʻohiʻona neorv32 no nā papa Intel FPGA e hoʻohana ana iā Quartus II a me SEGGER Embedded Studio no RISC-V..
- 9
Image-Generator-for-FPGA-Evaluation-Board
Hoʻolālā i kahi mea hana kiʻi e hōʻike i kahi hiʻohiʻona alanui. Hiki ke hoʻohana ʻia ma ke ʻano he hoʻolālā kū hoʻokahi no ka mea hoʻoheheʻe kiʻi a i ʻole ma ke ʻano he mea hoʻohālike hoʻāʻo ʻana no kahi kaapuni ʻike ala.
- 7
- GNU General Public License v3.0
