Nā hale waihona puke i kākau ʻia ma Verilog

ice-chips-verilog

ʻO IceChips kahi waihona o nā mea hoʻokalakupua ʻokoʻa maʻamau ma Verilog.
  • 105
  • GNU General Public License v3.0 only

Haasoscope

Nā palapala, hoʻolālā, firmware, a me nā lako polokalamu no ka Haasoscope.
  • 104
  • MIT

cpus-caddr

Mīkini lisp MIT CADR FPGA - kākau hou ʻia i ka verilog hou - nā kāmaʻa a holo.
  • 99

riscv-ocelot

Ocelot: ʻO ka Berkeley Out-of-Order Machine Me ke kākoʻo V-EXT.
  • 98
  • BSD 3-clause "New" or "Revised"

colorlight-led-cube

64x64 LED Cube e pili ana i ka papa kalaiwa LED Colorlight 5a-75B.
  • 89
  • GNU General Public License v3.0 only

Gameboy_MiSTer

Gameboy no MiSTer.
  • 89

sdspi

SD-Card controller, me ka hoʻohana ʻana i kahi interface SPI i kaʻana like ʻia.
  • 88

OpenSERDES

Hoʻolālā kikohoʻe synthesizable no SerDes me ka hoʻohana ʻana i ka ʻenehana Skywater Open PDK 130 nm.
  • 87
  • GNU General Public License v3.0 only

riscv

Hoʻokō ʻo Verilog i kahi kumu RISC-V (na ataradov).
  • 82
  • BSD 3-clause "New" or "Revised"

rt

ʻO kahi Lako Paʻa piha ʻo Ray-Tracer (na tomverbeur).
  • 76

freepdk-45nm

ASIC Design Kit no FreePDK45 + Nangate no ka hoʻohana ʻana me mflowgen.
  • 76

dpll

ʻO kahi hōʻiliʻili o nā papahana pili i ka loop locked loop (PLL).
  • 76

xenowing

"He aha ka mea e hiki mai ana? Super Mario 128? ʻOiaʻiʻo, ʻo ia kaʻu makemake e hana. ".
  • 75
  • Apache License 2.0

basic-ecp5-pcb

Hoʻolālā kuhikuhi no Lattice ECP5 FPGA. E hōʻike ana i ka interface Raspberry Pi a me 6 PMOD.
  • 73
  • Creative Commons Zero v1.0 Universal

wbscope

ʻO kahi ākea i manaʻo ʻia no ka FPGA.
  • 65

panologic

PanoLogic Zero Client G1 ka ʻike ʻenekinia hoʻohuli.
  • 64

Hazard3

3-pae RV32IMACZb* kaʻina hana me ka debug.
  • 60
  • Apache License 2.0

verilog-65C02-microcode

65C02 microprocessor ma verilog, liʻiliʻi liʻiliʻi, hoʻemi ʻia ka helu pōʻai, asynchronous interface.
  • 58

MegaCD_MiSTer

Mega CD no MiSTer.
  • 57
  • GNU General Public License v3.0 only

airisc_core_complex

Fraunhofer IMS kaʻina hana. ʻO RISC-V ISA (RV32IM) me nā periperal hou no nā noi AI i hoʻokomo ʻia a me nā ʻike akamai.
  • 57
  • GNU General Public License v3.0

qspiflash

He pūʻulu o Wishbone Controlled SPI Flash Controllers.
  • 56

wokwi-verilog-gds-test

  • 55
  • Apache License 2.0

Bluster

Hoʻololi CPLD no A2000 Buster.
  • 55
  • GNU General Public License v3.0

opencpi

Wehe Component Portability Infrastructure.
  • 54
  • GNU General Public License v3.0

riscv-formal

RISC-V Formal Verification Framework (na YosysHQ).
  • 54
  • ISC

spam-1

ʻO ka Home Brew 8 Bit CPU Hardware Implementation me kahi Verilog simulation, kahi hui, kahi "C" Compiler a me kēia repo kekahi i kaʻu noiʻi a aʻo ʻana. E nānā pū i ka papahana Hackaday. IO. https://hackaday.io/project/166922-spam-1-8-bit-cpu.
  • 51
  • Mozilla Public License 2.0

FPGA_Book_Experiments

ʻO kaʻu mau papahana i hoʻopau ʻia mai ka puke "FPGA Prototyping by Verilog Examples" na Pong P. Chu.
  • 48
  • MIT

Examples

  • 45
  • MIT

clockport_pi_interface

ʻO ke awa uaki ʻo Amiga i ka interface Raspberry Pi.
  • 45
  • GNU General Public License v3.0 only

zerosoc

Demo SoC no SiliconCompiler..
  • 44