Nā hale waihona puke i kākau ʻia ma Verilog
Piccolo
RISC-V CPU, 3-stage pipeline maʻalahi, no nā noi haʻahaʻa (e laʻa, hoʻokomo ʻia, IoT) (na CTSRD-CHERI).
- 5
- Apache License 2.0
kasirga_gok_2023
Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı.
- 5
- GNU General Public License v3.0 only
Kiwi-Project-Samples
Nā papahana laʻana no ka uLab Kiwi FPGA + ESP32, a me nā papa hoʻomohala Kiwi Lite.
- 4
rv32-cpu
ʻO kaʻu hoʻāʻo kūleʻa mua i ke kūkulu ʻana i kahi CPU RISC-V..
- 2
- GNU General Public License v3.0 only
SDRAM_Controller_Verilog
ʻO kēia kaohi SDRAM no MT48LC32M16 SDRAM. Ua hoʻolālā ʻia kēia module ma lalo o ka manaʻo he 100MHz ka nui o ka uaki.
- 2
Verilog_UDP_TCP
ʻO ka Module i hāʻawi ʻia i ka IP/TCP+UDP. Loaʻa iā Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý..
- 1
- MIT
psram-tang-nano-9k
He mea hoʻoponopono PSRAM/HyperRAM kumu no Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA (na dominicbeesley).
- 1
- Apache License 2.0