Nā hale waihona puke i kākau ʻia ma Verilog

xfcp

ʻO ke kahua hoʻomalu FPGA hiki ke hoʻonui.
  • 44
  • MIT

zbasic

He iwi iwi ʻole, kumu, ʻōnaehana ZipCPU i hoʻolālā ʻia no ka hoʻāʻo ʻana a me ka hoʻohui wikiwiki ʻana i nā ʻōnaehana hou.
  • 38

interpolation

Hoʻohana ʻia nā ʻenehana Interpolation Digital i ka hana ʻana i ka hōʻailona kikohoʻe.
  • 37

Verilog_Calculator_Matrix_Multiplication

He papahana maʻalahi kēia e hōʻike ana pehea e hoʻonui ai i ʻelua matrixes 3x3 ma Verilog.
  • 37
  • Mozilla Public License 2.0

NTHU-ICLAB

清華大學 | 積體電路設計實驗 (IC LAB) | 110上.
  • 34

MiSTery

Atari ST/STe kumu no nā FPGA.
  • 30

demo-projects

Nā papahana demo no nā papa Kintex FPGA like ʻole (e openXC7).
  • 30
  • BSD 3-clause "New" or "Revised"

Arcade-TMNT_MiSTer

ʻO Konami's Teenage Mutant Ninja Turtles no ke kahua MiSTer FPGA.
  • 29
  • GNU General Public License v3.0 only

MiSTerFPGA_YC_Encoder

Hoʻopili ʻia nā hana āpau i ka YC / NTSC & PAL Encoder no MiSTerFPGA.
  • 29
  • MIT

fftdemo

He hōʻikeʻike e hōʻike ana i ka hiki ke hoʻopili ʻia nā ʻāpana e kūkulu i kahi spectrogram i hoʻohālikelike ʻia.
  • 28

neorv32-verilog

♻️ E hoʻohuli i ke kaʻina hana NEORV32 i loko o kahi module netlist plain-Verilog me ka hoʻohana ʻana iā GHDL..
  • 28
  • BSD 3-clause "New" or "Revised"

a2o

ʻO ke kumu A2O he mea hahai ia iā A2I, i kākau ʻia ma Verilog, a kākoʻo i ka helu haʻahaʻa haʻahaʻa ma mua o A2I, akā ʻoi aku ka kiʻekiʻe o ka hana ma kēlā me kēia pae, me ka hoʻohana ʻana i ka hoʻokō ʻana i waho (ka inoa inoa hou, nā kikowaena hoʻopaʻa inoa, hoʻopau paʻa) a me kahi hale kūʻai. laina laina. Ke hōʻano hou ʻia nei no ka hoʻokō ʻana a me ka hoʻohui ʻana i nā papahana wehe. (na OpenPOWERFoundation).
  • 27
  • GNU General Public License v3.0

FPGA_RealTime_and_Static_Sobel_Edge_Detection

Hoʻokō Pipelined o Sobel Edge Detection ma ke kāmela OV7670 a ma nā kiʻi paʻa.
  • 27
  • MIT

dbgbus

Kūkulu ʻia a hōʻike ʻia kahi hōʻiliʻili o nā buses debugging ma zipcpu.com.
  • 27

jt89

sn76489an kūpono ʻo Verilog core, me ka manaʻo nui i ka hoʻokō FPGA a me Megadrive/Master System compatibility.
  • 26
  • GNU General Public License v3.0 only

gateware

ʻO nā submodules IP, i hoʻopili ʻia no ka hoʻopili maʻalahi o ka CI.
  • 24
  • GNU General Public License v3.0

boxlambda

FPGA pahu pahu microcomputer no ka lako polokalamu a me ka hoʻokolohua RTL.
  • 24
  • MIT

psram-tang-nano-9k

ʻO kahi mea hoʻoponopono PSRAM/HyperRAM kumu wehe no Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA.
  • 24
  • Apache License 2.0

CPLD-Guide

Ke alakaʻi alakaʻi ʻana i nā mea hoʻopalekana programmable Logic Device (CPLD).
  • 21

FPGA_OV7670_Camera_Interface

ʻO ka hoʻoheheʻe manawa maoli o ka pahupaʻikiʻi OV7670 ma o VGA me kahi hoʻonā 640x480 ma 30fps.
  • 21
  • MIT

Rosebud

Hoʻolālā no FPGA-wikiwiki Middlebox Hoʻomohala.
  • 20
  • MIT

color3

ʻIke eeColor Color3 HDMI FPGA papa.
  • 19
  • MIT

RISC-V

Hoʻolālā hoʻolālā i ka RV32I Core ma Verilog HDL me ka hoʻonui Zicsr.
  • 19
  • MIT

ice40_power

Nānā mana o nā mea hana ICE40UP5K-SG48.
  • 18
  • MIT

arrowzip

He hōʻike hōʻike ZipCPU o ka papa MAX1000 FPGA.
  • 17

icozip

He awa hōʻike ZipCPU no ka icoboard.
  • 16

caravel_fulgor_opamp

Ho'āʻo Chip General Purpose OpAmp me Skywater SKY130 PDK.
  • 15
  • Apache License 2.0

FusionConverter

E hoʻolālā i nā faila no ka mea hoʻololi NeoGeo MVS i AES.
  • 15
  • GNU General Public License v3.0 only

dyract

ʻO DyRACT Open Source waihona.
  • 14

cia-verilog

Ka hoʻokō ʻana o 8250 Complex Interface Adapter (CIA) ma Verilog.
  • 14